The integration on a common semiconductor substrate of different electronic devices, such as traditional transistors and non-volatile memory cells with a double polysilicon level for example, presents the problem of reconciling the different needs for sealing these two different types of electronic devices. Sealing refers to the manufacturing process where one or more layers are formed after the polysilicon layer forming the gate regions of the transistors and memory cells have been formed. This manufacturing process seals these electronic devices.
Typically, memory cells undergo a high quality sealing step to ensure the retention properties of the charge stored in the floating gate region. For transistors, a protection layer formed as part of this sealing step is to provide protection from the subsequent process steps.
A prior art approach provides the use of two different photolithographic masks to first define the gate regions in a memory matrix, and then those of the circuitry even if the order is not significant. Afterwards, the simultaneous oxidation of both electronic devices occurs, thus sealing the devices by a single sealing layer.
Although advantageous, this approach has several drawbacks as the size of the electronic devices decreases. In fact, the continuous reduction in the size of the electronic devices pushes transistors to require thinner sealing layers, and heat treatments with lower temperatures. This is in contrast to memory cells requiring thicker layers in addition to higher quality requirements.
In addition, CMOS transistors may be formed on the same semiconductor substrate where memory cells are formed. However, in the treatments most commonly used in CMOS transistor manufacturing process etching, the oxide layer is used to seal the memory cells. This reduces the retention properties of the charge stored in the floating gate region.